State of Open Con 2025

Exploring 10 years of certified hardware so far, discussing the next 10 years to come.

Chip design workflows, particularly with hardware languages like SystemVerilog and UVM, face challenges due to limited high-quality training data for generative AI. This results in large language models (LLMs) struggling to provide accurate, context-aware assistance. This session introduces a framework that leverages open-source tools like Verible, Slang, and UVMLint to address these challenges. The multi-agent system improves hardware code development through iterative feedback loops and supports targeted UVM code reviews with a noise-reducing linting approach. This approach enhances LLM performance, improving development efficiency and code quality in semiconductor design.

We’ll talk about the latest developments in building commercial automotive grade ICs using an open source toolchain, including safety considerations like ISO26262

Tutorial on how to create your own SoC from purely open-source IP. This is based on lowRISC's Sonata system which we built using IP from multiple sources such as OpenTitan and Microsoft repositories.