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Tuesday February 4, 2025 1:35pm - 2:15pm GMT
Chip design workflows, particularly with hardware languages like SystemVerilog and UVM, face challenges due to limited high-quality training data for generative AI. This results in large language models (LLMs) struggling to provide accurate, context-aware assistance. This session introduces a framework that leverages open-source tools like Verible, Slang, and UVMLint to address these challenges. The multi-agent system improves hardware code development through iterative feedback loops and supports targeted UVM code reviews with a noise-reducing linting approach. This approach enhances LLM performance, improving development efficiency and code quality in semiconductor design.
Speakers
avatar for Deepa Palaniappan

Deepa Palaniappan

DAV Engineer, AsFigo Technologies
Deepa Palaniappan (deepa@asfigo.com) is a seasoned engineer working on multiple disciplines in IC design and verification. Her interests include open-source simulators such as Verilator, Icarus and libraries/frameworks such as GO2UVM, SVUnit etc. She contributes to few open-source projects such as SVA IP on Verilator... Read More →
AK

Ajeetha Kumari Venkatesan

Director of Verification, AsFigo
I am serving as Director of Verification at AsFigo (https://www.asfigo.com), a UK-based chip design start-up specializing in open-source chip designs. I also concurrently continue to run my other 2 ventures one on EdTech and the other a consulting company based out of Bangalore, India.My main contributions to open source in recent years are UVMLint, SVALint... Read More →
Tuesday February 4, 2025 1:35pm - 2:15pm GMT
Doddington Forum 1

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