State of Open Con 2025

Chip design workflows, particularly with hardware languages like SystemVerilog and UVM, face challenges due to limited high-quality training data for generative AI. This results in large language models (LLMs) struggling to provide accurate, context-aware assistance. This session introduces a framework that leverages open-source tools like Verible, Slang, and UVMLint to address these challenges. The multi-agent system improves hardware code development through iterative feedback loops and supports targeted UVM code reviews with a noise-reducing linting approach. This approach enhances LLM performance, improving development efficiency and code quality in semiconductor design.