I am serving as Director of Verification at AsFigo (
https://www.asfigo.com), a UK-based chip design start-up specializing in open-source chip designs. I also concurrently continue to run my other 2 ventures one on EdTech and the other a consulting company based out of Bangalore, India.
My main contributions to open source in recent years are UVMLint, SVALint, yoYoLint (
https://github.com/AsFigo/yoYoLint), and PySlint (
https://github.com/AsFigo/PySlint) - all are SystemVerilog linters. I have also co-authored few books including a free eBook on UVM (
https://tinyurl.com/uvmpdf), SVA Handbook (
https://www.systemverilog.us/sva_info.html), Pragmatic approach to VMM (
https://www.systemverilog.us/vmm_info.html), PSL (
https://www.systemverilog.us/psl_info.html).
I serve in various technical conferences as a technical reviewer such as DVCon (
https://www.dvcon-india.org) in India, China, etc. I've been a regular presenter at various forums across Europe this year including OSDA (
https://osda.ws/) (Valencia, Spain), RISC-V Summit Europe(
https://riscv.org/event/risc-v-summit-europe-2024/) (Munich, Germany), [OSMOSIS](
https://eda.sw.siemens.com/en-US/eda-events/osmosis-2024/) (Munich), and ORConf (
https://fossi-foundation.org/orconf/2024#our-10th-orconf) (Gothenburg, Sweden). I have earlier presented at similar events in USA, India.
