Deepa Palaniappan (
deepa@asfigo.com) is a seasoned engineer working on multiple disciplines in IC design and verification. Her interests include open-source simulators such as Verilator, Icarus and libraries/frameworks such as GO2UVM, SVUnit etc. She contributes to few open-source projects such as SVA IP on Verilator, MathLib development etc. She is consulting on FPGA design and verification to remote clients based in Europe.
